1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device which includes MOS transistors and has input and output protection circuits built therein.
2. Description of the Related Art
In a semiconductor integrated circuit device such as, for example, a MOSLSI, in order to prevent possible breakdown of an internal circuit element thereof by a surge of static electricity or the like applied to an input/output terminal (abbreviation of an input terminal or output terminal) thereof, an input/output protection circuit (abbreviation of an input protection circuit or output protection circuit) is provided between an input/output terminal and an internal circuit. Generally, an input protection circuit and an output protection circuit are each formed from a CMOS circuit wherein an N-channel transistor N1 and a P-channel transistor P1 are connected in series between a power supply potential VDD and a ground potential GND as seen in FIGS. 15(a) and 15(b), respectively.
Meanwhile, in a MOS transistor which forms a semiconductor integrated circuit device in recent years, in order to realize high integration and high speed operation, the gate electrode is formed finely to a dimension of half micron or less and a gate insulating film is formed as a thin film of 10 to 20 nm or less.
Further, in order to reduce the resistance of a diffused layer of the source and the drain or of the gate electrode, a metal silicide technique is employed. By a metal silicide technique, the resistance of the diffused layer is reduced from 100 to 200 .OMEGA./.mu.m.sup.2 to 5 to 10 .OMEGA./.mu.m.sup.2, that is, to approximately one twentieth.
A plan view of the input/output protection circuit shown in FIGS. 15(a) or 15(b) where it is formed on a semiconductor substrate using MOS transistors formed using the metal silicide technique is shown in FIG. 16 while sectional views taken along line A--A and line B--B in FIG. 16 are shown in FIGS. 17(a) and 17(b), respectively. Referring to FIGS. 16, 17(a) and 17(b), a P well 2A is provided on a surface of a P-type silicon semiconductor substrate 1, and the N-channel transistor is formed on the P well 2A and includes N.sup.+ -type diffused layers 3A and 3B, an N.sup.- -type diffused layer 4, a gate insulating film 5, side wall spacers 6 and gate electrodes 7N made of a polycrystalline silicon layer. The P-channel transistor is formed from an N well 8A, P.sup.+ -type diffused layers 9A and 9B, a P.sup.- -type diffused layer 10, the gate insulating film 5, the side wall spacers 6 and gate electrodes 7P. Further, in order to connect a GND terminal 17 to the P well 2A and connect a VDD terminal 19 to the N well 8A, a P.sup.+ diffused layer 9C and an N.sup.+ diffused layer 3C are formed, respectively. For example, a titanium silicide layer 11 is formed on the surfaces of the diffused layers 3A, 3B and and 9A, 9B and 9C by conversion into metal silicide. A field oxide film 12A isolates the N-channel transistor, the P-channel transistor and grounding portions of the wells from each other. An inter-layer insulating film 13 has contact holes 14NS, 14ND, 14NW, 14PS, 14PD and 14PW formed therein on the N.sup.+ -type diffused layers 3A, 3B, 3C, 9A, 9B and 9C, and metal electrodes 15NS, 15ND, 15NW, 15PS, 15PD and 15PW of the first layer are formed in the contact holes 14NS, 14ND, 14NW, 14PS, 14PD and 14PW, respectively. Similarly, the gate electrodes 7N and 7P are connected to metal wires 30N and 30P, respectively, of the second layer which selectively covers over an inter-layer insulating film not shown.
The N.sup.+ -type diffused layer 3A which provides source regions for the four N-channel transistors is individually connected to the metal electrodes 15NS, connected to the metal electrodes 15PW which are connected to the P.sup.+ diffused layer 9C which is the contact region of the P well 2A, and further connected to the GND terminal 17. The N.sup.+ -type diffused layer 3B which provides the drain regions for the N-channel transistors is connected commonly by the metal electrodes 15ND similarly and connected to either one of an input terminal IN (refer to FIG. 15(a)) and an output terminal OUT (refer to FIG. 15(b)). The gate electrodes 7N of the N-channel transistors are connected to either one of the GND terminal 17 (refer to FIG. 15(a)) and an internal element not shown (refer to FIG. 15(b)) by the metal wire 30N.
The P.sup.+ -type diffused layer 9A which provides source regions for the four P-channel transistors is individually connected to the metal electrodes 15PS, connected to the metal electrodes 15NW which are connected to the N.sup.+ diffused layer 3C which is the contact region of the N well 8A, and further connected to the VDD terminal 19. The P.sup.+ -type diffused layer 9B which provides the drain regions for the N-channel transistors is connected commonly by the metal electrodes 15PD similarly and connected to either one of the input terminal IN (refer to FIG. 15(a)) and the output terminal OUT (refer to FIG. 15(b)). The gate electrodes 7P of the P-channel transistors are connected to either one of the VDD terminal 19 (refer to FIG. 15(a)) and another internal element not shown (refer to FIG. 15(b)) by the metal wires 30P.
Operation when an external surge is applied to an input/output terminal 18 is described now. A strength test of an electrostatic breakdown withstanding voltage by an external surge is performed such that a testing apparatus is connected to the output terminal 18 and a positive or negative surge is applied to the GND terminal 17 and the VDD terminal 19. First, when a surge is applied as a negative voltage to the GND terminal 17, since this acts as a forward voltage to the PN junction between the N.sup.+ -type diffused layer 3B and the P well 2A, the forward PN junction is turned on. Then, the surge passes from the GND terminal 17 through the P.sup.+ diffused layer 9C, P well 2A and N.sup.+ -type diffused layer 3B and flows to the input/output terminal 18. Then, when a surge is applied as a positive voltage to the GND terminal 17, since this corresponds to a case wherein a positive voltage is applied to the drains with respect to the sources of the N-channel transistors, breakdown occurs at locations immediately below end portions of the gates adjacent the drains, that is, at locations of the N.sup.- -type diffused layer 4, by a potential difference between the drain regions (3B) and the gate electrodes 7N of the N-channel transistors. After the breakdown, current flows from the drain regions (N.sup.+ -type diffused layer 3B) to the P well 2A. Thus, the current raises the potential at the P well 2A to a positive potential, and as a result, a forward voltage is applied to the PN junctions between the P well 2A and the source regions (N.sup.+ -type diffused layer 3A) and the PN junctions are turned on. Consequently, the current flows from the drain regions (N.sup.+ -type diffused layer 3B) to the source regions (N.sup.+ -type diffused layer 3A). In other words, NPN parasitic bipolar transistors wherein the collectors are provided by the drain regions (N.sup.+ -type diffused layer 3B), the bases are provided by the P well 2A and the emitters are provided by the N.sup.+ -type diffused layer 3A are turned on, and consequently, the surge flows from the input/output terminal 18 through the N.sup.+ -type diffused layer 3B, P well 2A and N.sup.+ -type diffused layer 3A to the GND terminal 17. Then, when a surge is applied as a positive voltage to the VDD terminal 19, since the PN junction between the P.sup.+ -type diffused layer 9B and the N well 8A is turned on by a forward voltage, the surge flows from the input/output terminal 18 through the P.sup.+ -type diffused layer 9B, N well 8A and N.sup.+ diffused layer 3C to the VDD terminal 19. When a surge is applied as a negative voltage to the VDD terminal 19, a phenomenon similar to that which occurs with the N-channel transistors as described above occurs with the P-channel transistors, and PNP parasitic transistors formed from the drain region (P.sup.+ -type diffused layer 9B), N well 8A and source region (P.sup.30 -type diffused layer 9A) are turned on. Consequently, the surge flows from the VDD terminal 19 through the P.sup.+ -type diffused layer 9A, N well 8A and P.sup.+ -type diffused layer 9B to the input/output terminal 18.
As described above, when an external surge is applied to the input/output terminal 18, the surge is discharged as current flows between the input/output terminal 18 and the GND terminal 17 or the VDD terminal 19, thereby protecting the internal circuit elements.
On the other hand, if an external surge is applied as a positive voltage to the GND terminal 17 or applied as a negative voltage to the VDD terminal 19, the NPN or PNP parasitic bipolar transistors are turned on to allow current to flow between the sources and the drains of the transistors. In this instance, however, heat is generated by resistances between the sources and the drains. In order to prevent melting or breakdown of the heat generating portions by the thus generated heat, that is, in order to increase the allowable amount of the on-current, a transistor of an input/output protection circuit generally has a large gate width of several hundreds microns. A transistor having such a large gate width is actually formed from a plurality of transistors arranged in parallel to each other and designed such that, in a layout thereof on a plane, they have an equal gate width 29 as seen in FIG. 16.
It is described above that, in the conventional semiconductor device described above, if an external surge is applied as a positive voltage to the GND terminal 17 or applied as a negative voltage to the VDD terminal 19, parasitic bipolar transistors are turned on and current flows between the sources and the drains of the transistors. Here, if notice is taken of a case wherein a surge is applied as a positive voltage to the GND terminal 17, the current to voltage characteristic of the drain with respect to the source of the N-channel transistors is such as illustrated in FIG. 18. Further, a route along which the current flows in FIG. 18 is shown in FIG. 19. In FIG. 18, if the drain voltage becomes equal to a breakdown voltage VB of the transistors by a surge, then breakdown occurs at locations immediately below end portions of the gates adjacent the drains. Thereafter, current flows from the drain regions toward the P well along a current route A of FIG. 19, and when a point given by V1, I1 is reached, the PN junctions between the P well and the source regions are turned on. Consequently, current flows along the drain region.fwdarw.P well.fwdarw.source region of a current route B of FIG. 19, and the voltage snaps back to a snap-back voltage VS. After the snap-back, the voltage and the current increase with an inclination defined by a sum total of a resistance of a metal wire between the input/output terminal 18 and the drain regions (N.sup.+ -type diffused layer 3B), a diffused layer resistance of the drain regions (N.sup.+ -type diffused layer 3B), a P well resistance between the drain regions (N.sup.+ -type diffused layer 3B) and the source regions (N.sup.+ -type diffused layer 3A), a diffused layer resistance of the regions (N.sup.+ -type diffused layer 3A) and a resistance of a wire between the source regions (N.sup.+ -type diffused layer 3A) and the GND terminal 17. V2 and I2 represent a voltage and a current, respectively, at which the transistors are broken down by heat generation when the voltage and the current increase.
Of the resistances which contribute to the increases of the voltage and the current after the snap-back mentioned above, the metal wire resistances are as low as several .OMEGA., and also the P well resistance between the drain regions (N.sup.+ -type diffused layer 3B) and the source regions (N.sup.+ -type diffused layer 3A) when the bipolar transistors are turned on is approximately several .OMEGA. per 100 .mu.m of the gate width. The diffused layer resistances of the drain regions (N.sup.+ -type diffused layer 3B) and the source regions (N.sup.+ -type diffused layer 3A) are as high as several hundreds .OMEGA. absent the surface titanium silicide layer, but as a result of conversion into titanium silicide, also they are as low as approximately several .OMEGA.. Accordingly, since the total resistance is approximately several tens .OMEGA., the voltage increase until the transistor is broken down after the snap-back is small, and as a result, the relationship of VS&lt;V2&lt;VB&lt;V1 is obtained. According to an example of actual evaluation, V2 of the transistor wherein VB was 15 V, VI was 15.5 V and VS was 10 V was 12 V.
Here, a first problem arises from the relationship of V2&lt;VB. In particular, if only one of a plurality of divisional transistors shown in FIG. 16 breaks down due to an offset in timing at which a surge flows, then the drain voltage increases only to V2 in the maximum after it snaps back to VS of the transistor, and consequently, the drain voltages of the remaining transistors do not reach the breakdown voltage and no breakdown occurs with the remaining transistors. As a result, since the surge flows only through the single transistor which has broken down first, if the surge exceeds the electrostatic breakdown withstanding voltage of the single transistor, breakdown by remarkable heat generation occurs and the input/output protection circuit loses its function.
The second problem resides in that the life of the transistor is deteriorated by hot carriers produced by the current I1. This is a phenomenon that breakdown of a transistor occurs at a location immediately below an end portion of the gate adjacent the drain region (N.sup.+ -type diffused layer 3B) and, when the current which thereafter flows passes by the gate insulating film, hot carriers are produced and caught by the gate insulating film, thereby causing a drop of the current of the transistor and further causing dielectric breakdown of the gate insulating film. This phenomenon arises from the current while the voltage increases from VB to V1, and when the voltage is V1, the current is in the maximum at I1.
While the foregoing description is given taking notice of the N-channel transistors, also with the P-channel transistors, problems similar to the first and second problems described above are caused by a similar phenomenon.